1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same and, in particular, to a semiconductor device and a method for manufacturing the same, wherein etching is carried out without any accompanying damage to a less-durable resist used during ArF-photolithography and, in turn, a problem is solved concerning Line Edge Roughness (LER; also referred to as “striation”) permitting the formation of fine patterns of not more than 130 nm while ensuring a high degree of accuracy. The present invention likewise relates to a dry-etching process which permits etching without any accompanying damage of a less-durable resist used during ArF-photolithography as well as a method for making electrical connections by making use of the dry-etching process.
2. Description of the Related Art
Recently, the structural details of semiconductor devices have gradually become finer and finer and the layer structure thereof has included more and more layers as the integration density of LSI devices has increased and the operational speed thereof has become higher and higher. The light-exposure methods used in the production of these LSI devices frequently include methods using lasers, each emitting a beam having a short wavelength (for instance, an excimer laser). An example is ArF-photolithography. A mask pattern is transferred onto a resist material consisting of, for instance, a methacrylic resin or an acrylic resin to form a resist mask. Then, a film covered by the resist mask is finely processed by dry-etching to give holes or grooves for the formation of electrical connections. In such fine processing, a high processing accuracy is required in the formation of such an etching pattern while ensuring high accuracy in both the width and depth directions of the film. For this reason, etching has been carried out while ensuring a high anisotropy of the etching technique. Accordingly, a technique has been known in which dry-etching is carried out while introducing a desired etching gas into the plasma atmosphere (see, for instance, Patent Document 1 specified below).
Compounds free of any benzene ring have been known as a resist material used in ArF-photolithography. These compounds impart to the resist material permeability to light rays whose wavelengths fall within the range of vacuum ultraviolet light rays (see, for instance, Non-Patent Document 1 specified below).
When this resist material is exposed to the ArF laser light rays or beam, not only does the material become less-durable but also shows a reduced resistance (durability) to plasma as compared with the resist material possessing a benzene ring used as a resist material for KrF-photolithography. Thus, when etching is carried out in a plasma atmosphere, the resist mask prepared therefrom is exposed to an etchant present in the plasma. Consequently, the resulting resist mask suffers from various problems such that the edge portions of the patterned regions are roughened, and the periphery of the resulting pattern is deformed due to the influence of the ultraviolet light rays and the bombardment of the ions originated from the plasma discharge.
The attached FIGS. 15(a) to (c) and (a′) to (c′) are schematic cross-sectional and top-plan views of semiconductor devices provided for illustrating a method for the preparation of gates for the transistors present in a conventional semiconductor device. In a conventional gate-forming method, an oxide film 152 as shown in FIGS. 15(a) and (a′) is grown on a substrate 151 of Si to a desired film thickness. A laminate film 153 consisting of a polysilicon film 153a and a tungsten film 153b is, for instance, formed thereon as a film for forming the gate electrodes. Then, an electrical insulating film 154 of SiO2 for forming a hard mask is formed (or deposited) according to any known method, such as the CVD technique. Then, an anti-reflection film 155 is coated and formed, followed by the application or formation of a resist 156 (for instance, TARF-P6111 available from Tokyo Ohka Kogyo Co., Ltd.) for ArF-photolithography mainly comprising an acrylic resin. The resist film 156 thus formed is exposed to light rays using a known ArF-photolithography apparatus (such as TWINSCAN-XT1400 available from ASML Company) to form a resist mask 156 having a pattern corresponding to the desired gate electrodes on the laminate film 153 for forming such gate electrodes. In this connection, thin films generally used for such a hard mask include, for instance, electrical insulating films such as SiN films and SiC films prepared by CVD technique.
When the hard mask electrical insulating film 154, covered with the resist mask 156 carrying the pattern, is subjected to dry-etching in a plasma atmosphere to transfer the pattern onto the electrical insulating film 154 through the resist mask 156, the edges of the pattern are often distorted, the shape of the pattern is, in turn, deformed, and a part of the resist becomes thin and sometimes perforated (LER of the resist). If etching is continued using the resist mask carrying such defects, various problems arise. For instance, the hard mask is likewise distorted and/or deformed and the pattern, whose periphery has defects, is transferred. This leads to the occurrence of so-called striation as shown in FIGS. 15(b) and (b′). Thus, if dry-etching is further continued using the hard mask 154b, which causes such striation to thus transfer the damaged pattern onto the laminate film 153 for forming such gate electrodes through the hard mask 154b, the striation per se is transferred to the gate electrode-forming laminate film 153 as shown in FIGS. 15(c) and (c′). Such a striation may sometimes reach even a size on the order of 50 nm and, accordingly, this technique cannot satisfy requirements for highly precise processing through etching.
When this deformation called striation reaches even a size on the order of 50 nm, the resulting pattern may be acceptable as a line pattern if the pattern is so designed that it has a line width of 200 nm. However, if the line width is designed to be not more than 130 nm and there are defects having a width from the periphery of 50 nm, the resulting pattern having such a narrow remaining line width is not acceptable as compared with the designed line width. Accordingly, this patterning technique cannot be used for the manufacture of a semiconductor device provided thereof with a fine pattern.
As has been discussed above in detail, the material generally used for forming gates of transistors is polysilicon or a material having a laminate structure consisting of a polysilicon layer and a tungsten layer applied onto polysilicon layer. In this case, the gate length Lg is an important parameter for manufacturing transistor gates to determine the threshold voltage for distinguishing the on and off operations of a transistor. Therefore, the gate length should accurately be controlled. When striation or any deformation of the pattern edge is caused while etching the material for forming gates, a single gate would have a distribution of gate lengths Lg. This results in the formation of transistors having mixed long and short gate lengths Lg, in a parallel connection. Accordingly, the threshold voltage of the resulting transistor is broad and the transistor never shows sharp on-off characteristic properties.
When the threshold voltage of a transistor becomes broad, additional voltage is needed for operating the transistor. This accordingly leads to an increase in the design voltage of a power source. This would be attended by such a bad effect that the resulting device consumes a large quantity of electric power. Moreover, if there is a divergence in the median of the threshold voltage, it is necessary to design the transistor such that it has a long logic cycle to adjust the timing of the operations thereof. The resulting transistor cannot permit any high speed operation. Such a high voltage of the power source and such a slow logic cycle cannot satisfy the recent conditions required for the designation of goods, such as a high integration density, a high speed operability and a low power-consumption. Accordingly, it is quite important to carry out such processing while limiting the distribution of gate lengths Lg within a single gate to a level as low as possible.
Under such circumstances, control of the line width would be quite important in the gate-forming step. When a pattern is transferred onto a resist layer by ArF-photolithography and then a gate material is directly etched through the resist pattern as a mask, the resist as a mask should be so designed to have a thickness considerably greater than that of the material to be etched. When the resist is so designed, the depth of focus (DOF) is smaller than the thickness of the resist. Accordingly, problems arise such that there are portions, which are out of focus, in the deeper region within the resist and, therefore, an accurate pattern cannot be transferred. As a method for eliminating this problem, conventionally a resist pattern is transferred onto a hard mask having high resistance to any etching operation through a thin resist serving as a mask. When the thickness of the resist is reduced, however, additional problems arise such that a striation is caused when etching such a hard mask and that each single gate has a distribution of gate lengths Lg.
When producing copper electrical connections (also hereafter referred to as Cu-connections) according to conventional ArF-photolithography and etching, for instance, the single damascene method, an SiO2 film 162a is deposited on the transistor-forming region 161 by the CVD technique. An SiN film 162b is then deposited thereon as an etching-stopper layer. An SiO2 film 162c is further deposited, and a second SiN film 162d is deposited thereon as a CMP-stopper layer to thus form an interlayer insulating (dielectric) film 162 as shown in FIG. 16(a). Then, an ArF-resist mask (not shown) carrying an electrical connection pattern is formed on the interlayer dielectric film 162 according to known ArF-photolithography, such as for the above-described gate-forming method. Then, the interlayer dielectric film 162 covered with this resist mask for the ArF-photolithography is subjected to dry-etching within a plasma atmosphere for the transfer of the electrical connection pattern into the interlayer dielectric film 162 to form grooves and holes to be filled with a metal electrical connection material. A barrier metal layer such as a TaN film 163 is formed on and/or within the grooves and holes thus formed according to any known sputtering technique and then a Cu film is formed by the Cu-plating technique to fill the grooves and holes with the metal electrical connection material. Finally, a Cu-electrical connection 164 is completed likewise by any known CMP method.
When forming the Cu-connection 164 in this way, while applying the conventional pattern-transfer technique, striations are generated, for instance, on and/or within the grooves and holes as shown in FIG. 16(b). For this reason, deep constricted parts 165 are formed at the edges of the pattern of holes and/or grooves present on the SiO2 film 162c constituting the interlayer dielectric film as shown in FIG. 16(c) and a sufficient amount of the barrier metal 163 cannot penetrate into the grooves and/or holes. Various problems arise such as insufficient barrier characteristic properties. The Cu 164 serving as an electrical connection material may penetrate and diffuse into the thin film to cause short circuits between electrical connections in proximity to one another. If the extent of this short circuit-formation is quite light, this becomes a cause of current leakage. The variation of the short circuit-formation with the elapse of time may become a cause of marketing defects of the resulting articles. In this respect, the term “marketing defects of articles” herein used means that an article having a semiconductor device is considered damaged during its circulation in the marketplace.
If narrow portions are only partially present in the electrical connections, the connections are quite liable to breakage. For this reason, the width of the electrical connection is increased at the time of its design to prevent any reduction of the width of such a narrower portion to a level of less than the predetermined level. However, the tip area of the resulting semiconductor device correspondingly increases. This may reduce the number of designed tips per wafer and, in turn, increase the production cost thereof. Accordingly, it would be necessary to manufacture articles which have low scattering in the finished line widths.
When subjecting an interlayer dielectric film (electrical insulating film) to dry-etching through a resist mask, the resist mask first undergoes deformation. The interlayer dielectric film is etched through the deformed resist mask and thereby transfers the deformation of the resist mask onto the dielectric film as the deformation of the film pattern (this deformation is so-called striation). The electrical connections of a semiconductor device are formed by filling the grooves in which the striation is generated with a barrier metal layer and a Cu film. Accordingly, the striations within the grooves are transferred as the striations of the electrical connections. The number of layers constituting the electrical connections of a semiconductor device is often ten or more in the case of, for instance, the usual system LSIs and memory devices. Accordingly, the reduction of such striations, which may result in the yield reduction, would be quite important to reduce the production cost.
In the case of the transfer of a pattern having line width and space between the neighboring lines of not less than 200 nm, the generation of striation can be controlled by the use of a material having a benzene ring as a mask for the layer of a resist for KrF-photolithography. The resist used in KrF-photolithography is highly resistant to irradiation with ultraviolet light rays emitted by the action of the plasma generated within a chamber for dry-etching and likewise to the fluorine radicals generated through the decomposition of C3F8 used as an etching gas. For this reason, when striation, which is irregular deformation of a resist, is relatively small, the design line width thereof is rather large as compared with the striation generated and therefore, a problem does not arise. In the case of the semiconductor devices of new generation, the line width and space between each pair of neighboring lines of not more than 130 nm and, in particular, not more than 100 nm are required. However, photolithography technique has been employed which makes use of an ArF laser. The resist used in this case would have a chemical structure quite sensitive to irradiation with ultraviolet light rays and fluorine radicals. Accordingly, the resulting striation is greater than that observed for the resist having a compound including a benzene ring used in the KrF-photolithography method. Therefore, a problem arises such that the rate of such striation relative to the line width becomes high and this, in turn, reduces the yield of the semiconductor device-manufacture.
To solve the foregoing problem concerning the generation of striations, a conventional technique has been proposed which comprises the steps of introducing a fluorocarbon gas-containing mixed gas into a low-pressure plasma atmosphere, forming a resist as a mask by ArF-photolithography and then subjecting a film (an interlayer dielectric film) to dry-etching through the resist as the mask (see, for instance, Patent Document 2 specified later). This technique would permit the control of the generation of striation by practicing the dry-etching at a low pressure. However, the technique is not a practical one from the economical standpoint since the etching rate is significantly reduced.    Patent Document 1: Japanese Un-Examined Patent Publication Hei 11-31678 (for instance, Claims);    Patent Document 2: Japanese Patent Application Serial No. 2004-56962 (Japanese Un-Examined Patent Publication 2005-251814) (for instance, Claims); and    Non-Patent Document 1: Koji NOZAKI and Ei YANO, FUJITSU Sei. Tech. J., 2002 (June), 38(1): 3-12.